From 00eadf9791dd7d5e11cbe03e775989e2c2485454 Mon Sep 17 00:00:00 2001
From: Alexander Boettcher <alexander.boettcher@genode-labs.com>
Date: Mon, 1 Nov 2021 14:07:52 +0100
Subject: [PATCH] vbox6: adjust TPR handling according to HMVMXR0

Issue #4313
---
 repos/ports/src/virtualbox6/sup_vcpu.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/repos/ports/src/virtualbox6/sup_vcpu.cc b/repos/ports/src/virtualbox6/sup_vcpu.cc
index 3e262a527f..0d2ca42c1a 100644
--- a/repos/ports/src/virtualbox6/sup_vcpu.cc
+++ b/repos/ports/src/virtualbox6/sup_vcpu.cc
@@ -254,8 +254,6 @@ template <typename VIRT> void Sup::Vcpu_impl<VIRT>::_transfer_state_to_vcpu(CPUM
 		const uint8_t tpr_priority = (tpr >> 4) & 0xf;
 		if (pending_priority <= tpr_priority)
 			state.tpr_threshold.charge(pending_priority);
-		else
-			state.tpr_threshold.charge(tpr_priority);
 	}
 
 	/* export FPU state */
@@ -563,6 +561,8 @@ typename Sup::Vcpu_impl<T>::Current_state Sup::Vcpu_impl<T>::_handle_irq_window(
 			if (RT_SUCCESS(rc)) {
 				rc = TRPMAssertTrap(pVCpu, irq, TRPM_HARDWARE_INT);
 				Assert(RT_SUCCESS(rc));
+			} else if (rc == VERR_APIC_INTR_MASKED_BY_TPR) {
+				state.tpr_threshold.charge(irq >> 4);
 			}
 		}