base: interface for D- and I-cache synchronization

On ARM, when machine instructions get written into the data cache
(for example by a JIT compiler), one needs to make sure that the
instructions get written out to memory and read from memory into
the instruction cache before they get executed. This functionality
is usually provided by a kernel syscall and this patch adds a generic
interface for Genode applications to use it.

Fixes #1153.

repos/base/include/cpu/cache.h

@@ -0,0 +1,28 @@
+/*
+ * \brief  Cache operations
+ * \author Christian Prochaska
+ * \date   2014-05-13
+ */
+
+/*
+ * Copyright (C) 2014 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU General Public License version 2.
+ */
+
+#ifndef _INCLUDE__CPU__CACHE_H_
+#define _INCLUDE__CPU__CACHE_H_
+
+#include <base/stdint.h>
+
+namespace Genode {
+
+	/*
+	 * Make D-Cache and I-Cache coherent
+	 */
+	void cache_coherent(Genode::addr_t addr, Genode::size_t size);
+
+}
+
+#endif /* _INCLUDE__CPU__CACHE_H_ */

repos/base/src/base/cpu/cache.cc

@@ -0,0 +1,21 @@
+/*
+ * \brief  Implementation of the cache operations
+ * \author Christian Prochaska
+ * \date   2014-05-13
+ */
+
+/*
+ * Copyright (C) 2014 Genode Labs GmbH
+ *
+ * This file is part of the Genode OS framework, which is distributed
+ * under the terms of the GNU General Public License version 2.
+ */
+
+#include <cpu/cache.h>
+
+/*
+ * This function needs to be implemented only for base platforms with ARM
+ * support right now, so the default implementation does nothing.
+ */
+void cache_coherent(Genode::addr_t, Genode::size_t) { }
+