From 4b10aa94ec1a29568d348c8bf98b8aa121015d44 Mon Sep 17 00:00:00 2001 From: Sebastian Sumpf Date: Fri, 2 Jul 2021 11:05:34 +0200 Subject: [PATCH] base-hw: save/restore fpcr register for ARM_V8 The floating-point (fpcr) control register is user land accessible and controls, for example, rounding mode. fixes #3723 and related to #4213 --- repos/base-hw/src/core/spec/arm_v8/cpu.h | 3 ++- repos/base-hw/src/core/spec/arm_v8/exception_vector.s | 8 +++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/repos/base-hw/src/core/spec/arm_v8/cpu.h b/repos/base-hw/src/core/spec/arm_v8/cpu.h index 143ed724e5..e249a5e440 100644 --- a/repos/base-hw/src/core/spec/arm_v8/cpu.h +++ b/repos/base-hw/src/core/spec/arm_v8/cpu.h @@ -56,7 +56,8 @@ struct Genode::Cpu : Hw::Arm_64_cpu struct alignas(16) Fpu_state { Genode::uint128_t q[32]; - Genode::uint32_t fpsr; + Genode::uint64_t fpsr; + Genode::uint64_t fpcr; }; struct alignas(8) Context : Cpu_state diff --git a/repos/base-hw/src/core/spec/arm_v8/exception_vector.s b/repos/base-hw/src/core/spec/arm_v8/exception_vector.s index 2454b8a26d..ebd9b26eb1 100644 --- a/repos/base-hw/src/core/spec/arm_v8/exception_vector.s +++ b/repos/base-hw/src/core/spec/arm_v8/exception_vector.s @@ -60,8 +60,9 @@ _kernel_entry: stp q26, q27, [x0], #32 stp q28, q29, [x0], #32 stp q30, q31, [x0], #32 + mrs x1, fpcr mrs x2, fpsr - str x2, [x0] + stp x1, x2, [x0], #16 msr fpsr, xzr ldr x0, [sp, #-16] ldr x1, [sp, #-32] @@ -111,8 +112,9 @@ _kernel_entry: ldp q26, q27, [x1], #32 ldp q28, q29, [x1], #32 ldp q30, q31, [x1], #32 - ldr x1, [x1] - msr fpsr, x1 + ldp x2, x3, [x1], #16 + msr fpcr, x2 + msr fpsr, x3 add x0, x0, #8 ldp x1, x2, [x0], #16 ldp x3, x4, [x0], #16