diff --git a/repos/base-hw/src/core/spec/x86_64/pic.cc b/repos/base-hw/src/core/spec/x86_64/pic.cc index 8d24c240fb..12c29d4e9a 100644 --- a/repos/base-hw/src/core/spec/x86_64/pic.cc +++ b/repos/base-hw/src/core/spec/x86_64/pic.cc @@ -170,6 +170,9 @@ Irte::access_t Ioapic::_create_irt_entry(unsigned const irq) Ioapic::Ioapic() : Mmio(Platform::mmio_to_virt(Hw::Cpu_memory_map::MMIO_IOAPIC_BASE)) { + write(IOAPICVER); + _irte_count = read() + 1; + for (unsigned i = 0; i < IRQ_COUNT; i++) { /* set legacy/ISA IRQs to edge, high */ @@ -182,7 +185,7 @@ Ioapic::Ioapic() : Mmio(Platform::mmio_to_virt(Hw::Cpu_memory_map::MMIO_IOAPIC_B } /* remap all IRQs managed by I/O APIC */ - if (i < IRTE_COUNT) { + if (i < _irte_count) { Irte::access_t irte = _create_irt_entry(i); write(IOREDTBL + 2 * i + 1); write(irte >> Iowin::ACCESS_WIDTH); @@ -198,7 +201,7 @@ void Ioapic::toggle_mask(unsigned const vector, bool const set) /* * Ignore toggle requests for vectors not handled by the I/O APIC. */ - if (vector < REMAP_BASE || vector >= REMAP_BASE + IRTE_COUNT) { + if (vector < REMAP_BASE || vector >= REMAP_BASE + _irte_count) { return; } diff --git a/repos/base-hw/src/core/spec/x86_64/pic.h b/repos/base-hw/src/core/spec/x86_64/pic.h index 595ad9f4e9..c5af1aef46 100644 --- a/repos/base-hw/src/core/spec/x86_64/pic.h +++ b/repos/base-hw/src/core/spec/x86_64/pic.h @@ -53,12 +53,10 @@ class Genode::Ioapic : public Mmio enum { REMAP_BASE = Board::VECTOR_REMAP_BASE }; - uint8_t _irt_count; + /* Number of Redirection Table entries */ + unsigned _irte_count; enum { - /* Number of Redirection Table entries */ - IRTE_COUNT = 24, - /* Register selectors */ IOAPICVER = 0x01, IOREDTBL = 0x10, @@ -130,7 +128,10 @@ class Genode::Ioapic : public Mmio */ struct Ioregsel : Register<0x00, 32> { }; - struct Iowin : Register<0x10, 32> { }; + struct Iowin : Register<0x10, 32> + { + struct Maximum_redirection_entry : Bitfield<16, 8> { }; + }; }; class Genode::Pic : public Mmio