diff --git a/repos/os/src/drivers/framebuffer/spec/omap4/driver.h b/repos/os/src/drivers/framebuffer/spec/omap4/driver.h
index c15a6c0823..fcb7dc3488 100644
--- a/repos/os/src/drivers/framebuffer/spec/omap4/driver.h
+++ b/repos/os/src/drivers/framebuffer/spec/omap4/driver.h
@@ -250,11 +250,13 @@ bool Framebuffer::Driver::_init_hdmi(Framebuffer::addr_t phys_base)
 	_dispc.write<Dispc::Control1::Tv_enable>(1);
 	_dispc.write<Dispc::Control1::Go_tv>(1);
 
-	if (!_dispc.wait_for<Dispc::Control1::Go_tv>(Dispc::Control1::Go_tv::HW_UPDATE_DONE, _delayer)) {
+	try {
+		_dispc.wait_for(_delayer, Dispc::Control1::Go_tv::Equal(Dispc::Control1::Go_tv::HW_UPDATE_DONE));
+	}
+	catch (Dispc::Polling_timeout) {
 		error("Go_tv timed out");
 		return false;
 	}
-
 	return true;
 }
 
diff --git a/repos/os/src/drivers/framebuffer/spec/omap4/hdmi.h b/repos/os/src/drivers/framebuffer/spec/omap4/hdmi.h
index 3df0aba19f..c16a0f6846 100644
--- a/repos/os/src/drivers/framebuffer/spec/omap4/hdmi.h
+++ b/repos/os/src/drivers/framebuffer/spec/omap4/hdmi.h
@@ -77,14 +77,28 @@ struct Hdmi : Genode::Mmio
 	{
 		write<Pwr_ctrl::Pll_cmd>(cmd);
 
-		return wait_for<Pwr_ctrl::Pll_status>(cmd, delayer);
+		try {
+			wait_for(delayer, Pwr_ctrl::Pll_status::Equal(cmd));
+		}
+		catch (Polling_timeout) {
+			Genode::error("Pwr_ctrl::Pll_cmd failed");
+			return false;
+		}
+		return true;
 	}
 
 	bool issue_pwr_phy_command(Pwr_ctrl::Phy_cmd_type cmd, Delayer &delayer)
 	{
 		write<Pwr_ctrl::Phy_cmd>(cmd);
 
-		return wait_for<Pwr_ctrl::Phy_status>(cmd, delayer);
+		try {
+			wait_for(delayer, Pwr_ctrl::Phy_status::Equal(cmd));
+		}
+		catch (Polling_timeout) {
+			Genode::error("unexpected Pwr_ctrl::Phy_status");
+			return false;
+		}
+		return true;
 	}
 
 	struct Pll_control : Register<0x200, 32>
@@ -105,8 +119,15 @@ struct Hdmi : Genode::Mmio
 
 	bool wait_until_pll_locked(Delayer &delayer)
 	{
-		return wait_for<Pll_status::Pll_locked>(1, delayer);
-	};
+		try {
+			wait_for(delayer, Pll_status::Pll_locked::Equal(1));
+		}
+		catch (Polling_timeout) {
+			Genode::error("Pll_locked::Pll_locked unexpectedly not set");
+			return false;
+		}
+		return true;
+	}
 
 	struct Pll_go : Register<0x208, 32>
 	{
@@ -118,8 +139,14 @@ struct Hdmi : Genode::Mmio
 		write<Pll_go::Go>(1);
 
 		/* wait for PLL_GO bit change and the PLL reaching locked state */
-		return wait_for<Pll_go::Go>(1, delayer)
-		    && wait_until_pll_locked(delayer);
+		try {
+			wait_for(delayer, Pll_go::Go::Equal(1));
+		}
+		catch (Polling_timeout) {
+			Genode::error("Pll_go::Go unexpectedly not set");
+			return false;
+		}
+		return wait_until_pll_locked(delayer);
 	}
 
 	struct Cfg1 : Register<0x20c, 32>
@@ -147,7 +174,14 @@ struct Hdmi : Genode::Mmio
 	{
 		write<Pll_control::Reset>(0);
 
-		return wait_for<Pll_status::Reset_done>(1, delayer);
+		try {
+			wait_for(delayer, Pll_status::Reset_done::Equal(1));
+		}
+		catch (Polling_timeout) {
+			Genode::error("Pll_status::Reset_done unexpectedly not set");
+			return false;
+		}
+		return true;
 	};
 
 	struct Txphy_tx_ctrl : Register<0x300, 32>