From 6789b868713ccd3fed4d4652f24d49d3e6a367ff Mon Sep 17 00:00:00 2001 From: Stefan Kalkowski Date: Thu, 23 Sep 2021 16:34:23 +0200 Subject: [PATCH] base-hw: optimize cache maintainance for ARMv8 * Remove the data-synchronization barrier from the inner-loop * Instead add a system-wide barrier at the end of the operation Fix #4269 --- repos/base-hw/src/core/spec/arm_v8/cpu.cc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/repos/base-hw/src/core/spec/arm_v8/cpu.cc b/repos/base-hw/src/core/spec/arm_v8/cpu.cc index 9586a8dd54..a06e142f1b 100644 --- a/repos/base-hw/src/core/spec/arm_v8/cpu.cc +++ b/repos/base-hw/src/core/spec/arm_v8/cpu.cc @@ -121,12 +121,12 @@ void Genode::Cpu::cache_clean_invalidate_data_region(addr_t const base, Genode::memory_barrier(); auto lambda = [] (addr_t const base) { - asm volatile("dc civac, %0" :: "r" (base)); - asm volatile("dsb ish"); - asm volatile("isb"); - }; + asm volatile("dc civac, %0" :: "r" (base)); }; cache_maintainance(base, size, lambda); + + asm volatile("dsb sy"); + asm volatile("isb"); } @@ -136,12 +136,12 @@ void Genode::Cpu::cache_invalidate_data_region(addr_t const base, Genode::memory_barrier(); auto lambda = [] (addr_t const base) { - asm volatile("dc ivac, %0" :: "r" (base)); - asm volatile("dsb ish"); - asm volatile("isb"); - }; + asm volatile("dc ivac, %0" :: "r" (base)); }; cache_maintainance(base, size, lambda); + + asm volatile("dsb sy"); + asm volatile("isb"); }