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Remove zynq_qemu platform and zynq nic driver

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Moved to separate repo at https://github.com/jschlatow/genode-zynq

Fixes genodelabs/genode#4280
This commit is contained in:
Johannes Schlatow
2021-10-04 13:09:03 +02:00
committed by Christian Helmuth
parent 6ecae6adb3
commit 7917c5d9ec
36 changed files with 6 additions and 2899 deletions
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68
repos/base/include/drivers/defs/zynq.h
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@@ -1,68 +0,0 @@
/*
* \brief MMIO and IRQ definitions common to Xilinx Zynq platforms
* \author Mark Albers
* \author Timo Wischer
* \author Johannes Schlatow
* \date 2014-12-15
*/
/*
* Copyright (C) 2014-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__ZYNQ_H_
#define _INCLUDE__DRIVERS__DEFS__ZYNQ_H_
namespace Zynq {
enum {
/* device IO memory */
MMIO_0_BASE = 0xe0000000, /* IOP devices */
MMIO_0_SIZE = 0x10000000,
MMIO_1_BASE = 0xF8000000, /* Programmable register via APB */
MMIO_1_SIZE = 0x02000000,
QSPI_MMIO_BASE = 0xFC000000, /* Quad-SPI */
QSPI_MMIO_SIZE = 0x01000000,
OCM_MMIO_BASE = 0xFFFC0000, /* OCM upper address range */
OCM_MMIO_SIZE = 0x00040000,
/* normal RAM */
RAM_0_BASE = 0x00000000,
/* AXI */
AXI_0_MMIO_BASE = 0x40000000, /* PL AXI Slave port #0 */
AXI_0_MMIO_SIZE = 0x40000000,
AXI_1_MMIO_BASE = 0x80000000, /* PL AXI Slave port #1 */
AXI_1_MMIO_SIZE = 0x40000000,
/* UART controllers */
UART_0_MMIO_BASE = MMIO_0_BASE,
UART_SIZE = 0x1000,
UART_CLOCK = 50*1000*1000,
/* CPU */
CORTEX_A9_PRIVATE_MEM_BASE = 0xf8f00000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
/* entrypoint address of secondary cpu */
CORE1_ENTRY = 0xfffffff0,
/* CPU cache */
PL310_MMIO_BASE = MMIO_1_BASE + 0xF02000,
PL310_MMIO_SIZE = 0x1000,
/* TTC (triple timer counter) */
TTC0_MMIO_BASE = MMIO_1_BASE + 0x1000,
TTC0_MMIO_SIZE = 0xfff,
TTC0_IRQ_0 = 42,
/* Ethernet MAC PS */
EMAC_0_MMIO_BASE = 0xE000B000,
EMAC_0_MMIO_SIZE = 0x1000,
EMAC_0_IRQ = 54,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__ZYNQ_H_ */

31
repos/base/include/drivers/defs/zynq_qemu.h
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@@ -1,31 +0,0 @@
/*
* \brief Base driver for the Zynq (QEMU)
* \author Johannes Schlatow
* \date 2015-06-30
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__ZYNQ_QEMU_H_
#define _INCLUDE__DRIVERS__DEFS__ZYNQ_QEMU_H_
#include <drivers/defs/zynq.h>
namespace Zynq_qemu {
using namespace Zynq;
enum {
RAM_0_SIZE = 0x40000000, /* 1GiB */
CORTEX_A9_PRIVATE_TIMER_CLK = 100000000,
CORTEX_A9_PRIVATE_TIMER_DIV = 100,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__ZYNQ_QEMU_H_ */

129
repos/base/include/drivers/uart/xilinx.h
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@@ -1,129 +0,0 @@
/*
* \brief Base UART driver for the Xilinx UART PS used on Zynq devices
* \author Johannes Schlatow
* \date 2014-12-15
*/
/*
* Copyright (C) 2014-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__UART__XILINX_H_
#define _INCLUDE__DRIVERS__UART__XILINX_H_
/* Genode includes */
#include <util/mmio.h>
namespace Genode { class Xilinx_uart; }
/**
* Base driver Xilinx UART PS module
*/
class Genode::Xilinx_uart: public Mmio
{
protected:
/**
* Control register
*/
struct Uart_cr : Register<0x00, 32>
{
struct Rx_reset : Bitfield<0, 1> { };
struct Tx_reset : Bitfield<1, 1> { };
struct Rx_enable : Bitfield<2, 1> { };
struct Tx_enable : Bitfield<4, 1> { };
};
/**
* Mode register
*/
struct Uart_mr : Register<0x04, 32>
{
struct Clock_sel : Bitfield<0, 1> { };
struct Parity : Bitfield<3, 3> { enum { NO_PARITY = 4 }; };
};
/**
* Baudgen register
*/
struct Uart_baudgen : Register<0x18, 32>
{
struct Clock_div : Bitfield<0, 16> { };
};
/**
* Status register
*/
struct Uart_sr : Register<0x2C, 32>
{
struct Tx_full : Bitfield<4, 1> { };
};
/**
* FIFO register
*/
struct Uart_fifo : Register<0x30, 32>
{
struct Data : Bitfield<0, 8> { };
};
/**
* Bauddiv register
*/
struct Uart_bauddiv : Register<0x34, 32>
{
struct Bdiv : Bitfield<0,8> { };
};
public:
/**
* Constructor
*
* \param base MMIO base address
* \param clock reference clock
* \param baud_rate targeted baud rate
*/
Xilinx_uart(addr_t const base, unsigned long const clock,
unsigned long const baud_rate) : Mmio(base)
{
/* reset UART */
Uart_cr::access_t uart_cr = 0;
Uart_cr::Tx_reset::set(uart_cr, 1);
Uart_cr::Rx_reset::set(uart_cr, 1);
write<Uart_cr>(uart_cr);
/* set baud rate */
constexpr unsigned div = 4;
write<Uart_bauddiv::Bdiv>(div);
write<Uart_baudgen::Clock_div>(clock / baud_rate / (div + 1));
/* set 8N1 */
Uart_mr::access_t uart_mr = 0;
Uart_mr::Parity::set(uart_mr, Uart_mr::Parity::NO_PARITY);
write<Uart_mr>(uart_mr);
/* enable */
uart_cr = 0;
Uart_cr::Rx_enable::set(uart_cr, 1);
Uart_cr::Tx_enable::set(uart_cr, 1);
write<Uart_cr>(uart_cr);
}
/**
* Transmit ASCII char 'c'
*/
void put_char(char const c)
{
/* wait as long as the transmission buffer is full */
while (read<Uart_sr::Tx_full>()) ;
/* transmit character */
write<Uart_fifo::Data>(c);
}
};
#endif /* _INCLUDE__DRIVERS__UART__XILINX_H_ */