hw: re-organize file structure

fix #1197
This commit is contained in:
Martin Stein
2014-07-09 12:03:17 +02:00
committed by Norman Feske
parent bfdc4138ba
commit a5cf09fa6e
151 changed files with 1935 additions and 2599 deletions

View File

@@ -14,26 +14,23 @@
#ifndef _INCLUDE__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__DRIVERS__BOARD_BASE_H_
/* Genode includes */
#include <platform_exynos5/board_base.h>
namespace Genode
{
/**
* Board driver base
*/
struct Board_base
struct Board_base : Exynos5
{
enum
{
/* normal RAM */
RAM_0_BASE = 0x40000000,
RAM_0_SIZE = 0x80000000,
/* device IO memory */
MMIO_0_BASE = 0x10000000,
MMIO_0_SIZE = 0x10000000,
/* clock management unit */
CMU_MMIO_BASE = 0x10010000,
CMU_MMIO_SIZE = 0x24000,
/* power management unit */
PMU_MMIO_BASE = 0x10040000,
PMU_MMIO_SIZE = 0x5000,
@@ -46,17 +43,6 @@ namespace Genode
UART_2_CLOCK = 100000000,
UART_2_IRQ = 85,
/* timer */
PWM_MMIO_BASE = 0x12dd0000,
PWM_MMIO_SIZE = 0x1000,
PWM_CLOCK = 66000000,
PWM_IRQ_0 = 68,
MCT_MMIO_BASE = 0x101c0000,
MCT_MMIO_SIZE = 0x1000,
MCT_CLOCK = 24000000,
MCT_IRQ_L0 = 152,
MCT_IRQ_L1 = 153,
/* USB */
USB_HOST20_IRQ = 103,
USB_DRD30_IRQ = 104,
@@ -70,9 +56,6 @@ namespace Genode
/* SD card */
SDMMC0_IRQ = 107,
/* CPU cache */
CACHE_LINE_SIZE_LOG2 = 6,
/* wether board provides security extension */
SECURITY_EXTENSION = 1,
@@ -86,4 +69,3 @@ namespace Genode
}
#endif /* _INCLUDE__DRIVERS__BOARD_BASE_H_ */

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@@ -14,23 +14,18 @@
#ifndef _INCLUDE__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__DRIVERS__BOARD_BASE_H_
/* Genode includes */
#include <platform_exynos5/board_base.h>
namespace Genode
{
/**
* Board driver base
*/
struct Board_base
struct Board_base : Exynos5
{
enum
{
/* normal RAM */
RAM_0_BASE = 0x40000000,
RAM_0_SIZE = 0x80000000,
/* device IO memory */
MMIO_0_BASE = 0x10000000,
MMIO_0_SIZE = 0x10000000,
/* interrupt controller */
GIC_CPU_MMIO_BASE = 0x10481000,
GIC_CPU_MMIO_SIZE = 0x00010000,
@@ -40,16 +35,6 @@ namespace Genode
UART_2_CLOCK = 62668800,
UART_2_IRQ = 85,
/* timer */
PWM_MMIO_BASE = 0x12dd0000,
PWM_MMIO_SIZE = 0x1000,
PWM_CLOCK = 66000000,
PWM_IRQ_0 = 68,
MCT_MMIO_BASE = 0x101c0000,
MCT_MMIO_SIZE = 0x1000,
MCT_CLOCK = 24000000,
MCT_IRQ_L0 = 152,
/* CPU cache */
CACHE_LINE_SIZE_LOG2 = 6,
@@ -60,4 +45,3 @@ namespace Genode
}
#endif /* _INCLUDE__DRIVERS__BOARD_BASE_H_ */

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@@ -0,0 +1,56 @@
/*
* \brief Board-driver base
* \author Stefan Kalkowski
* \date 2013-11-25
*/
/*
* Copyright (C) 2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _EXYNOS5__BOARD_BASE_H_
#define _EXYNOS5__BOARD_BASE_H_
namespace Genode
{
/**
* Board-driver base
*/
class Exynos5;
}
class Genode::Exynos5
{
public:
enum {
/* normal RAM */
RAM_0_BASE = 0x40000000,
RAM_0_SIZE = 0x80000000,
/* device IO memory */
MMIO_0_BASE = 0x10000000,
MMIO_0_SIZE = 0x10000000,
/* pulse-width-modulation timer */
PWM_MMIO_BASE = 0x12dd0000,
PWM_MMIO_SIZE = 0x1000,
PWM_CLOCK = 66000000,
PWM_IRQ_0 = 68,
/* multicore timer */
MCT_MMIO_BASE = 0x101c0000,
MCT_MMIO_SIZE = 0x1000,
MCT_CLOCK = 24000000,
MCT_IRQ_L0 = 152,
MCT_IRQ_L1 = 153,
/* CPU cache */
CACHE_LINE_SIZE_LOG2 = 6,
};
};
#endif /* _EXYNOS5__BOARD_BASE_H_ */