From be7df4fa82304e450eb54fa409e4fc86bafc1c7c Mon Sep 17 00:00:00 2001 From: Christian Helmuth Date: Wed, 22 Jan 2025 12:41:28 +0100 Subject: [PATCH] fixup "hw: always serialize rdtsc reads" (final cosmetic touches) --- .../src/bootstrap/spec/x86_64/platform.cc | 27 +++++++++---------- .../src/include/hw/spec/x86_64/x86_64.h | 3 ++- 2 files changed, 14 insertions(+), 16 deletions(-) diff --git a/repos/base-hw/src/bootstrap/spec/x86_64/platform.cc b/repos/base-hw/src/bootstrap/spec/x86_64/platform.cc index 9af5c04954..8ec2e444ac 100644 --- a/repos/base-hw/src/bootstrap/spec/x86_64/platform.cc +++ b/repos/base-hw/src/bootstrap/spec/x86_64/platform.cc @@ -131,7 +131,7 @@ static void disable_pit() PIT_MODE = 0x43, }; - /** + /* * Disable PIT timer channel. This is necessary since BIOS sets up * channel 0 to fire periodically. */ @@ -142,12 +142,11 @@ static void disable_pit() /* - * Enable dispatch serializing lfence instruction on AMD processors. + * Enable dispatch serializing lfence instruction on AMD processors * - * See: - * Software techniques for managing speculation on AMD processors - * Revision 5.09.23 - * Mitigation G-2 + * See Software techniques for managing speculation on AMD processors + * Revision 5.09.23 + * Mitigation G-2 */ static void amd_enable_serializing_lfence() { @@ -158,14 +157,12 @@ static void amd_enable_serializing_lfence() unsigned const family = Hw::Vendor::get_family(); - /* In family 0Fh and 11h, lfence is always dispatch serializing */ - if ((family == 0x10) || - (family == 0x12) || - /* - * "AMD plans support for this MSR and access to this bit for all - * future processors." - */ - (family >= 0x14)) { + /* + * In family 0Fh and 11h, lfence is always dispatch serializing and + * "AMD plans support for this MSR and access to this bit for all future + * processors." from family 14h on. + */ + if ((family == 0x10) || (family == 0x12) || (family >= 0x14)) { Cpu::Amd_lfence::access_t amd_lfence = Cpu::Amd_lfence::read(); Cpu::Amd_lfence::Enable_dispatch_serializing::set(amd_lfence); Cpu::Amd_lfence::write(amd_lfence); @@ -358,7 +355,7 @@ Bootstrap::Platform::Board::Board() } /* - * Enable serializing lfence on supported AMD processors. + * Enable serializing lfence on supported AMD processors * * For APs this will be set up later, but we need it already to obtain * the most acurate results when calibrating the TSC frequency. diff --git a/repos/base-hw/src/include/hw/spec/x86_64/x86_64.h b/repos/base-hw/src/include/hw/spec/x86_64/x86_64.h index b3e40fc70f..91817ad5f9 100644 --- a/repos/base-hw/src/include/hw/spec/x86_64/x86_64.h +++ b/repos/base-hw/src/include/hw/spec/x86_64/x86_64.h @@ -110,7 +110,8 @@ public: struct Hw::Tsc { /* - * Provide serialized access to the Timestamp Counter. + * Provide serialized access to the Timestamp Counter + * * See #5430 for more information. */ static Genode::uint64_t rdtsc()