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hw & cortex_a9: fix scheduling-timer speed

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The estimation of the input clock of the Cortex A9 Private Timer module
was pretty miserable at every Cortex A9 board.

Fixes #1341
This commit is contained in:
Martin Stein
2015-01-06 13:30:07 +01:00
committed by Christian Helmuth
parent ba321c20d1
commit e63092f1dd
5 changed files with 9 additions and 18 deletions
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5
repos/base/include/platform/panda/drivers/board_base.h
View File

@@ -34,8 +34,7 @@ namespace Genode
RAM_0_SIZE = 0x40000000,
/* clocks */
MPU_DPLL_CLOCK = 200*1000*1000,
SYS_CLK = 38400000,
SYS_CLK = 38400000,
/* UART controllers */
TL16C750_1_MMIO_BASE = MMIO_0_BASE + 0x6a000,
@@ -58,7 +57,7 @@ namespace Genode
/* CPU */
CORTEX_A9_PRIVATE_MEM_BASE = 0x48240000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
CORTEX_A9_CLOCK = MPU_DPLL_CLOCK,
CORTEX_A9_PRIVATE_TIMER_CLK = 350000000,
/* L2 cache */
PL310_MMIO_BASE = 0x48242000,

7
repos/base/include/platform/pbxa9/drivers/board_base.h
View File

@@ -44,12 +44,11 @@ namespace Genode
/* clocks */
OSC_6_CLOCK = 24*1000*1000,
OSC_7_CLOCK = 14*1000*1000,
/* CPU */
CORTEX_A9_CLOCK = OSC_7_CLOCK * 5,
CORTEX_A9_PRIVATE_MEM_BASE = 0x1f000000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x01000000,
CORTEX_A9_PRIVATE_TIMER_CLK = 100000000,
CORTEX_A9_PRIVATE_MEM_BASE = 0x1f000000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x01000000,
/* UART */
PL011_0_MMIO_BASE = 0x10009000,

9
repos/base/include/platform/vea9x4/drivers/board_base.h
View File

@@ -65,9 +65,6 @@ namespace Genode
PL180_0_IRQ = 9,
PL180_1_IRQ = 10,
/* clocks */
TCREF_CLOCK = 66670*1000,
/* TrustZone Address Space Controller */
TZASC_MMIO_BASE = 0x100ec000,
TZASC_MMIO_SIZE = 0x1000,
@@ -77,9 +74,9 @@ namespace Genode
TZPC_MMIO_SIZE = 0x1000,
/* CPU */
CORTEX_A9_PRIVATE_MEM_BASE = 0x1e000000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
CORTEX_A9_CLOCK = TCREF_CLOCK,
CORTEX_A9_PRIVATE_MEM_BASE = 0x1e000000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
CORTEX_A9_PRIVATE_TIMER_CLK = 200010000,
/* wether board provides security extension */
SECURITY_EXTENSION = 1,