riscv: Use Qemu and update to ISA v1.10

- remove Spike/BBL support in favour of Qemu (>=4.2.1)
- add 'riscv_qemu' board, remove 'spike' board'
- update to privileged ISA v1.10 (from v1.9.1)
- use direct system calls for privileged core threads (they call into
  the kernel and don't use mode changing system calls, i.e. 'ecall',
  semantics)
- use 'OpenSBI' semtantics for SBI calls (to machine mode) instead of
  BBL

issue #4012

repos/base/include/drivers/defs/riscv.h

@@ -1,25 +0,0 @@
-/*
- * \brief  MMIO and IRQ definitions for RISC-V (1.9.1)
- * \author Sebastian Sumpf
- * \date   2017-05-29
- */
-
-/*
- * Copyright (C) 2013-2017 Genode Labs GmbH
- *
- * This file is part of the Genode OS framework, which is distributed
- * under the terms of the GNU Affero General Public License version 3.
- */
-
-#ifndef _INCLUDE__DRIVERS__DEFS__RISCV_H_
-#define _INCLUDE__DRIVERS__DEFS__RISCV_H_
-
-namespace Riscv {
-	enum {
-		RAM_0_BASE = 0x81000000,
-		RAM_0_SIZE = 0x6e00000,
-	};
-}
-
-#endif /* _INCLUDE__DRIVERS__DEFS__RISCV_H_ */
-