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riscv: Use Qemu and update to ISA v1.10

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- remove Spike/BBL support in favour of Qemu (>=4.2.1)
- add 'riscv_qemu' board, remove 'spike' board'
- update to privileged ISA v1.10 (from v1.9.1)
- use direct system calls for privileged core threads (they call into
  the kernel and don't use mode changing system calls, i.e. 'ecall',
  semantics)
- use 'OpenSBI' semtantics for SBI calls (to machine mode) instead of
  BBL

issue #4012
This commit is contained in:
Sebastian Sumpf
2021-02-10 08:31:39 +01:00
committed by Norman Feske
parent 18e282ab8a
commit fd0e6685fc
46 changed files with 393 additions and 453 deletions
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