riscv: Use Qemu and update to ISA v1.10

- remove Spike/BBL support in favour of Qemu (>=4.2.1)
- add 'riscv_qemu' board, remove 'spike' board'
- update to privileged ISA v1.10 (from v1.9.1)
- use direct system calls for privileged core threads (they call into
  the kernel and don't use mode changing system calls, i.e. 'ecall',
  semantics)
- use 'OpenSBI' semtantics for SBI calls (to machine mode) instead of
  BBL

issue #4012

tool/run/image/bbl

@@ -1,6 +0,0 @@
-proc run_image {elf_img} {
-	puts "using '$elf_img' as bbl image"
-
-	exec rm -f bbl/image.o
-	exec -ignorestderr make IMAGE_ELF=[pwd]/$elf_img bbl
-}