riscv: Use Qemu and update to ISA v1.10

- remove Spike/BBL support in favour of Qemu (>=4.2.1)
- add 'riscv_qemu' board, remove 'spike' board'
- update to privileged ISA v1.10 (from v1.9.1)
- use direct system calls for privileged core threads (they call into
  the kernel and don't use mode changing system calls, i.e. 'ecall',
  semantics)
- use 'OpenSBI' semtantics for SBI calls (to machine mode) instead of
  BBL

issue #4012

tool/run/log/spike

@@ -1,34 +0,0 @@
-
-source [genode_dir]/tool/run/log.inc
-source [genode_dir]/tool/run/spike.inc
-
-
-proc run_log { wait_for_re timeout_value } {
-	global spike_spawn_id
-	global output_spawn_id
-
-	set kernel_msg [run_boot_string]
-	set output_spawn_id $spike_spawn_id
-
-	if {$wait_for_re == "forever"} {
-		set timeout -1
-	} else {
-		set timeout $timeout_value
-	}
-
-	expect {
-		-i $output_spawn_id $kernel_msg { }
-		eof         {
-			puts stderr "Aborting, received EOF"
-			return false
-		}
-		timeout     {
-			puts stderr "Boot process timed out"
-			close
-			return false
-		}
-	}
-
-	wait_for_output $wait_for_re $timeout_value $spike_spawn_id
-	return true
-}