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When building Genode for VEA9X4 as micro-hypervisor protected by the ARM TrustZone hardware we ran into limitations regarding our basic daily testing routines. The most significant is that, when speaking about RAM partitioning, the only available options are to configure the whole SRAM to be secure and the whole DDR-RAM to be non-secure or vice versa. The SRAM however provides only 32 MB which isn't enough for both a representative non-secure guest OS or a secure Genode that is still capable of passing our basic tests. This initiated our decision to remove the VEA9X4 TrustZone-support. Fixes #1351
84 lines
1.7 KiB
C++
84 lines
1.7 KiB
C++
/*
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* \brief Driver for the Versatile Express A9X4 board
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__DRIVERS__BOARD_BASE_H_
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#define _INCLUDE__DRIVERS__BOARD_BASE_H_
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namespace Genode
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{
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/**
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* Driver for the Versatile Express A9X4 board
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*
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* Implies the uATX motherboard and the CoreTile Express A9X4 daughterboard
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*/
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struct Board_base
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{
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enum
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{
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/* MMIO */
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MMIO_0_BASE = 0x10000000,
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MMIO_0_SIZE = 0x10000000,
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MMIO_1_BASE = 0x4C000000,
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MMIO_1_SIZE = 0x04000000,
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/* RAM */
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RAM_0_BASE = 0x60000000,
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RAM_0_SIZE = 0x20000000,
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RAM_1_BASE = 0x84000000,
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RAM_1_SIZE = 0x1c000000,
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RAM_2_BASE = 0x48000000,
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RAM_2_SIZE = 0x02000000,
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/* UART */
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PL011_0_MMIO_BASE = MMIO_0_BASE + 0x9000,
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PL011_0_MMIO_SIZE = 0x1000,
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PL011_0_CLOCK = 24*1000*1000,
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PL011_0_IRQ = 37,
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PL011_1_IRQ = 38,
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PL011_2_IRQ = 39,
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PL011_3_IRQ = 40,
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/* timer/counter */
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SP804_0_1_MMIO_BASE = MMIO_0_BASE + 0x11000,
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SP804_0_1_MMIO_SIZE = 0x1000,
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SP804_0_1_CLOCK = 1000*1000,
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SP804_0_1_IRQ = 34,
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/* PS2 */
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KMI_0_IRQ = 44,
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KMI_1_IRQ = 45,
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/* LAN */
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LAN9118_IRQ = 47,
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/* card reader */
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PL180_0_IRQ = 9,
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PL180_1_IRQ = 10,
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1e000000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
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CORTEX_A9_PRIVATE_TIMER_CLK = 200010000,
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/* wether board provides security extension */
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SECURITY_EXTENSION = 1,
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/* CPU cache */
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CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
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};
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};
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}
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#endif /* _INCLUDE__DRIVERS__BOARD_BASE_H_ */
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