mirror of
https://github.com/mmueller41/genode.git
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285 lines
7.2 KiB
C++
285 lines
7.2 KiB
C++
/*
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* \brief Regulator driver for clock management unit of Exynos4412 SoC
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* \author Alexy Gallardo Segura <alexy@uclv.cu>
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* \author Humberto Lopez Leon <humberto@uclv.cu>
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* \author Reinier Millo Sanchez <rmillo@uclv.cu>
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* \date 2015-04-30
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _CMU_H_
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#define _CMU_H_
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#include <regulator/consts.h>
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#include <regulator/driver.h>
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#include <drivers/board_base.h>
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#include <os/attached_mmio.h>
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#include <base/printf.h>
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using namespace Regulator;
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class Cmu : public Regulator::Driver,
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public Genode::Attached_mmio
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{
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private:
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static const Genode::uint16_t m_values[]; /* M values for frequencies */
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static const Genode::uint8_t p_values[]; /* P values for frequencies */
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static const Genode::uint8_t s_values[]; /* S values for frequencies */
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template <unsigned OFF>
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struct Pll_lock : Register<OFF, 32>
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{
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struct Pll_locktime : Register<OFF, 32>::template Bitfield<0, 20> { };
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static Genode::uint32_t max_lock_time(Genode::uint8_t pdiv) {
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return pdiv * 250; };
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};
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template <unsigned OFF>
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struct Pll_con0 : Register<OFF, 32>
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{
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struct S : Register<OFF, 32>::template Bitfield < 0, 3> { };
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struct P : Register<OFF, 32>::template Bitfield < 8, 6> { };
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struct M : Register<OFF, 32>::template Bitfield <16, 10> { };
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struct Locked : Register<OFF, 32>::template Bitfield <29, 1> { };
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struct Enable : Register<OFF, 32>::template Bitfield <31, 1> { };
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};
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/***********************
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** CMU CPU registers **
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***********************/
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typedef Pll_lock<4000> Apll_lock;
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typedef Pll_con0<0x4100> Apll_con0;
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struct Clk_src_cpu : Register<0x4200, 32>
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{
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struct Mux_core_sel : Bitfield<16, 1>
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{
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enum { MOUT_APLL, SCLK_MPLL};
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};
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};
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struct Clk_mux_stat_cpu : Register<0x4400, 32>
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{
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struct Core_sel : Bitfield<16, 3>
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{
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enum { MOUT_APLL = 0b1, SCLK_MPLL = 0b10 };
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};
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};
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struct Clk_div_cpu0 : Register<0x4500, 32>
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{
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/* Cpu0 divider values for frequencies 200 - 1400 */
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static const Genode::uint32_t values[];
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};
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struct Clk_div_cpu1 : Register<0x4504, 32>
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{
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/* Divider for cpu1 doesn't change */
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enum { FIX_VALUE = 32 };
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};
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struct Clk_div_stat_cpu0 : Register<0x4600, 32>
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{
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struct Div_core : Bitfield< 0, 1> {};
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struct Div_corem0 : Bitfield< 4, 1> {};
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struct Div_corem1 : Bitfield< 8, 1> {};
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struct Div_pheriph : Bitfield<12, 1> {};
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struct Div_atb : Bitfield<16, 1> {};
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struct Div_pclk_dbg : Bitfield<20, 1> {};
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struct Div_apll : Bitfield<24, 1> {};
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struct Div_core2 : Bitfield<28, 1> {};
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static bool in_progress(access_t stat_word)
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{
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return stat_word & (Div_core::bits(1) |
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Div_corem0::bits(1) |
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Div_corem1::bits(1) |
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Div_pheriph::bits(1) |
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Div_atb::bits(1) |
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Div_pclk_dbg::bits(1) |
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Div_apll::bits(1) |
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Div_core2::bits(1));
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}
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};
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struct Clk_div_stat_cpu1 : Register<0x4604, 32>
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{
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struct Div_copy : Bitfield<0, 1> { };
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struct Div_hpm : Bitfield<4, 1> { };
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static bool in_progress(access_t stat_word)
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{
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return stat_word & (Div_copy::bits(1) |
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Div_hpm::bits(1));
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}
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};
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/************************
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** CMU CORE registers **
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************************/
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typedef Pll_lock<0x0008> Mpll_lock;
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typedef Pll_con0<0x0108> Mpll_con0;
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struct Clk_src_dmc : Register<0x4200, 32>
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{
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struct Mux_mpll_sel : Bitfield<12, 1> { enum { XXTI, MPLL_FOUT_RGT }; };
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};
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struct Clk_gate_ip_dmc : Register<0x0900, 32> { };
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struct Clk_gate_ip_isp0 : Register<0x8800, 32> { };
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struct Clk_gate_ip_isp1 : Register<0x8804, 32> { };
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/*******************
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** CPU functions **
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*******************/
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Cpu_clock_freq _cpu_freq;
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void _cpu_clk_freq(unsigned long level)
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{
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PINF("Setting CPU frequency %lu\n",level);
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unsigned freq;
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switch (level) {
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case CPU_FREQ_200:
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freq = 0;
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break;
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case CPU_FREQ_400:
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freq = 1;
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break;
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case CPU_FREQ_600:
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freq = 2;
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break;
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case CPU_FREQ_800:
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freq = 3;
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break;
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case CPU_FREQ_1000:
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freq = 4;
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break;
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case CPU_FREQ_1200:
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freq = 5;
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break;
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case CPU_FREQ_1400:
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freq = 6;
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break;
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default:
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PWRN("Unsupported CPU frequency level %ld", level);
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PWRN("Supported values are 200, 400, 600, 800, 1000, 1200, 14000 MHz");
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PWRN("and 1, 1.2, 1.4, 1.6, 1.7 GHz");
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return;
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};
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/**
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* change clock divider values
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*/
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/* cpu0 divider */
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write<Clk_div_cpu0>(Clk_div_cpu0::values[freq]);
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while (Clk_div_stat_cpu0::in_progress(read<Clk_div_stat_cpu0>())) ;
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/* cpu1 divider */
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write<Clk_div_cpu1>(Clk_div_cpu1::FIX_VALUE);
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while (Clk_div_stat_cpu1::in_progress(read<Clk_div_stat_cpu1>())) ;
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/**
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* change APLL frequency
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*/
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/* change reference clock to MPLL */
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write<Clk_src_cpu::Mux_core_sel>(Clk_src_cpu::Mux_core_sel::SCLK_MPLL);
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while (read<Clk_mux_stat_cpu::Core_sel>()
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!= Clk_mux_stat_cpu::Core_sel::SCLK_MPLL) ;
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/* set lock time */
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unsigned pdiv = p_values[freq];
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write<Apll_lock::Pll_locktime>(Apll_lock::max_lock_time(pdiv));
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/* change P, M, S values of APLL */
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write<Apll_con0::P>(p_values[freq]);
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write<Apll_con0::M>(m_values[freq]);
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write<Apll_con0::S>(s_values[freq]);
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while (!read<Apll_con0::Locked>()) ;
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/* change reference clock back to APLL */
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write<Clk_src_cpu::Mux_core_sel>(Clk_src_cpu::Mux_core_sel::MOUT_APLL);
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while (read<Clk_mux_stat_cpu::Core_sel>()
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!= Clk_mux_stat_cpu::Core_sel::MOUT_APLL) ;
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_cpu_freq = static_cast<Cpu_clock_freq>(level);
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}
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public:
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/**
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* Constructor
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*/
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Cmu()
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: Genode::Attached_mmio(Genode::Board_base::CMU_MMIO_BASE,
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Genode::Board_base::CMU_MMIO_SIZE),
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_cpu_freq(CPU_FREQ_1400)
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{
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/**
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* Set default CPU frequency
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*/
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_cpu_clk_freq(_cpu_freq);
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}
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/********************************
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** Regulator driver interface **
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********************************/
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void level(Regulator_id id, unsigned long level)
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{
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switch (id) {
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case CLK_CPU:
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_cpu_clk_freq(level);
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break;
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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}
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unsigned long level(Regulator_id id)
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{
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switch (id) {
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case CLK_CPU:
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return _cpu_freq;
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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return 0;
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}
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void state(Regulator_id id, bool enable)
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{
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}
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bool state(Regulator_id id)
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{
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return true;
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}
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};
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const Genode::uint8_t Cmu::s_values[] = { 2, 1, 1, 0, 0, 0, 0, 0, 0 };
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const Genode::uint16_t Cmu::m_values[] = { 100, 100, 200, 100, 125,
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150, 175, 200, 425 };
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const Genode::uint8_t Cmu::p_values[] = { 3, 3, 4, 3, 3, 3, 3, 3, 6 };
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const Genode::uint32_t Cmu::Clk_div_cpu0::values[] = { 0x1117710, 0x1127710, 0x1137710,
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0x2147710, 0x2147710, 0x3157720,
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0x4167720};
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#endif /* _CMU_H_ */
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