base-hw: Remove 'riscv_qemu' and move to 'genode-riscv'

issue #4312

repos/base-hw/board/riscv_qemu/arch

@@ -1 +0,0 @@
-riscv

repos/base-hw/board/riscv_qemu/image_link_address

@@ -1 +0,0 @@
-0x80200000

repos/base-hw/lib/mk/spec/riscv/bootstrap-hw-riscv_qemu.mk

@@ -1,10 +0,0 @@
-INC_DIR += $(REP_DIR)/src/bootstrap/board/riscv_qemu
-
-SRC_CC  += bootstrap/spec/riscv/platform.cc
-SRC_S   += bootstrap/spec/riscv/crt0.s
-SRC_CC  += lib/base/riscv/kernel/interface.cc
-SRC_CC  += spec/64bit/memory_map.cc
-
-vpath spec/64bit/memory_map.cc $(REP_DIR)/src/lib/hw
-
-include $(REP_DIR)/lib/mk/bootstrap-hw.inc

repos/base-hw/lib/mk/spec/riscv/core-hw-riscv_qemu.mk

@@ -1,27 +0,0 @@
-REP_INC_DIR += src/core/spec/riscv src/core/board/riscv_qemu
-
-CC_OPT += -fno-delete-null-pointer-checks
-
-# add C++ sources
-SRC_CC += platform_services.cc
-SRC_CC += kernel/vm_thread_off.cc
-SRC_CC += kernel/cpu_up.cc
-SRC_CC += kernel/lock.cc
-SRC_CC += spec/riscv/kernel/thread.cc
-SRC_CC += spec/riscv/kernel/cpu.cc
-SRC_CC += spec/riscv/kernel/interface.cc
-SRC_CC += spec/riscv/kernel/pd.cc
-SRC_CC += spec/riscv/cpu.cc
-SRC_CC += spec/riscv/pic.cc
-SRC_CC += spec/riscv/platform_support.cc
-SRC_CC += spec/riscv/timer.cc
-SRC_CC += spec/64bit/memory_map.cc
-
-#add assembly sources
-SRC_S += spec/riscv/exception_vector.s
-SRC_S += spec/riscv/crt0.s
-
-vpath spec/64bit/memory_map.cc $(call select_from_repositories,src/lib/hw)
-
-# include less specific configuration
-include $(call select_from_repositories,lib/mk/core-hw.inc)

repos/base-hw/recipes/src/base-hw-riscv_qemu/content.mk

@@ -1 +0,0 @@
-include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc

repos/base-hw/recipes/src/base-hw-riscv_qemu/hash

@@ -1 +0,0 @@
-2021-11-29 065c3a960169cb275938c657083d377e8a86ad35

repos/base-hw/recipes/src/base-hw-riscv_qemu/used_apis

@@ -1,2 +0,0 @@
-base-hw
-base

repos/base-hw/src/bootstrap/board/riscv_qemu/board.h

@@ -1,25 +0,0 @@
-/*
- * \brief   RISC-V Qemu specific board definitions
- * \author  Stefan Kalkowski
- * \date    2017-02-20
- */
-
-/*
- * Copyright (C) 2017 Genode Labs GmbH
- *
- * This file is part of the Genode OS framework, which is distributed
- * under the terms of the GNU Affero General Public License version 3.
- */
-
-#ifndef _SRC__BOOTSTRAP__SPEC__RISCV_QEMU__BOARD_H_
-#define _SRC__BOOTSTRAP__SPEC__RISCV_QEMU__BOARD_H_
-
-#include <hw/spec/riscv/qemu_board.h>
-
-namespace Board { using namespace Hw::Riscv_board; }
-
-template <typename E, unsigned B, unsigned S>
-void Sv39::Level_x_translation_table<E, B, S>::_translation_added(addr_t, size_t)
-{ }
-
-#endif /* _SRC__BOOTSTRAP__SPEC__RISCV_QEMU__BOARD_H_ */

repos/base-hw/src/core/board/riscv_qemu/board.h

@@ -1,27 +0,0 @@
-/*
- * \brief  Board spcecification
- * \author Sebastian Sumpf
- * \date   2015-06-02
- */
-
-/*
- * Copyright (C) 2015-2017 Genode Labs GmbH
- *
- * This file is part of the Genode OS framework, which is distributed
- * under the terms of the GNU Affero General Public License version 3.
- */
-
-#ifndef _CORE__SPEC__RISCV_QEMU__BOARD_H_
-#define _CORE__SPEC__RISCV_QEMU__BOARD_H_
-
-/* base-hw internal includes */
-#include <hw/spec/riscv/qemu_board.h>
-
-/* base-hw Core includes */
-#include <spec/riscv/pic.h>
-#include <spec/riscv/cpu.h>
-#include <spec/riscv/timer.h>
-
-namespace Board { using namespace Hw::Riscv_board; }
-
-#endif /* _CORE__SPEC__RISCV_QEMU__BOARD_H_ */

repos/base-hw/src/core/board/riscv_qemu/plic.h

@@ -1,38 +0,0 @@
-/**
- * \brief  Platform-level interrupt controller layout (PLIC)
- * \author Sebastian Sumpf
- * \date   2021-03-05
- */
-
-/*
- * Copyright (C) 2021 Genode Labs GmbH
- *
- * This file is part of the Genode OS framework, which is distributed
- * under the terms of the GNU Affero General Public License version 3.
- */
-
-#ifndef _CORE__SPEC__RISCV_QEMU__PLIC_H_
-#define _CORE__SPEC__RISCV_QEMU__PLIC_H_
-
-namespace Board { class Plic; }
-
-struct Board::Plic : Genode::Mmio
-{
-		enum { NR_OF_IRQ = 32 };
-
-		struct Enable : Register_array<0x80, 32, 32, 1> { };
-		struct Id     : Register<0x1ff004, 32> { };
-
-		Plic(Genode::addr_t const base)
-		:
-			Mmio(base) { }
-
-		void enable(unsigned value, unsigned irq)
-		{
-			write<Enable>(value, irq);
-		}
-
-		void el(unsigned, unsigned) { }
-};
-
-#endif /* _CORE__SPEC__RISCV_QEMU__PLIC_H_ */

repos/base-hw/src/core/spec/riscv/timer.h

@@ -18,9 +18,6 @@
 #include <base/stdint.h>
 #include <kernel/types.h>
 
-/* base-hw internal includes */
-#include <hw/spec/riscv/qemu_board.h>
-
 namespace Board { class Timer; }
 
 

repos/base-hw/src/include/hw/spec/riscv/page_table.h

@@ -413,7 +413,7 @@ namespace Hw {
 	{
 		enum {
 			TABLE_LEVEL_X_SIZE_LOG2 = Sv39::SIZE_LOG2_4K,
-			CORE_VM_AREA_SIZE = 128 * 1024 * 1024,
+			CORE_VM_AREA_SIZE = 512 * 1024 * 1024,
 			CORE_TRANS_TABLE_COUNT =
 				_count(CORE_VM_AREA_SIZE, Sv39::SIZE_LOG2_1G) +
 				_count(CORE_VM_AREA_SIZE, Sv39::SIZE_LOG2_2M),

repos/base-hw/src/include/hw/spec/riscv/qemu_board.h

@@ -1,41 +0,0 @@
-/*
- * \brief   RISC-V Qemu specific board definitions
- * \author  Sebastian Sumpf
- * \author  Stefan Kalkowski
- * \date    2021-02-09
- */
-
-/*
- * Copyright (C) 2021 Genode Labs GmbH
- *
- * This file is part of the Genode OS framework, which is distributed
- * under the terms of the GNU Affero General Public License version 3.
- */
-
-#ifndef _SRC__INCLUDE__HW__SPEC__RISCV__QEMU_BOARD_H_
-#define _SRC__INCLUDE__HW__SPEC__RISCV__QEMU_BOARD_H_
-
-#include <hw/spec/riscv/boot_info.h>
-#include <hw/spec/riscv/page_table.h>
-#include <hw/spec/riscv/sbi.h>
-
-namespace Hw::Riscv_board {
-
-	enum {
-		RAM_BASE = 0x80020000,
-		RAM_SIZE = 0x7fe0000,
-		TIMER_HZ = 10000000,
-
-		PLIC_BASE = 0xc002000,
-		PLIC_SIZE = 0x200000,
-	};
-
-	enum { UART_BASE, UART_CLOCK };
-
-	struct Serial : Hw::Riscv_uart
-	{
-		Serial(Genode::addr_t, Genode::size_t, unsigned) { }
-	};
-}
-
-#endif /* _SRC__INCLUDE__HW__SPEC__RISCV__QEMU_BOARD_H_ */

repos/base/board/riscv_qemu/qemu_args

@@ -1,2 +0,0 @@
--m 128 -machine virt -cpu rv64,priv_spec=v1.10.0
--bios default

tool/builddir/build.conf/repos_riscv

@@ -0,0 +1,5 @@
+#
+# Board support for RISC-V Qemu / MiG-V
+#
+#REPOSITORIES += $(GENODE_DIR)/repos/riscv
+

tool/create_builddir

@@ -91,7 +91,7 @@ BUILD_CONF_ARM_V7   := run_arm_v7 run_boot_dir repos repos_arm_v7
 BUILD_CONF(arm_v6)  := $(BUILD_CONF_ARM_V6)
 BUILD_CONF(arm_v7a) := $(BUILD_CONF_ARM_V7)
 BUILD_CONF(arm_v8a) := run_arm_v8 run_boot_dir repos repos_arm_v8
-BUILD_CONF(riscv)   := run_riscv run_boot_dir repos
+BUILD_CONF(riscv)   := run_riscv run_boot_dir repos repos_riscv
 BUILD_CONF(x86_32)  := run_x86_32 $(BUILD_CONF_X86)
 BUILD_CONF(x86_64)  := run_x86_64 $(BUILD_CONF_X86)
 BUILD_CONF(linux)   := run_kernel_linux repos