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fixup "hw: always serialize rdtsc reads" (final cosmetic touches)

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This commit is contained in:
Christian Helmuth
2025-01-22 12:41:28 +01:00
parent 6793143d31
commit be7df4fa82
2 changed files with 14 additions and 16 deletions
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27
repos/base-hw/src/bootstrap/spec/x86_64/platform.cc
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@@ -131,7 +131,7 @@ static void disable_pit()
PIT_MODE = 0x43, PIT_MODE = 0x43,
}; };
/** /*
* Disable PIT timer channel. This is necessary since BIOS sets up * Disable PIT timer channel. This is necessary since BIOS sets up
* channel 0 to fire periodically. * channel 0 to fire periodically.
*/ */
@@ -142,12 +142,11 @@ static void disable_pit()
/* /*
* Enable dispatch serializing lfence instruction on AMD processors. * Enable dispatch serializing lfence instruction on AMD processors
* *
* See: * See Software techniques for managing speculation on AMD processors
* Software techniques for managing speculation on AMD processors * Revision 5.09.23
* Revision 5.09.23 * Mitigation G-2
* Mitigation G-2
*/ */
static void amd_enable_serializing_lfence() static void amd_enable_serializing_lfence()
{ {
@@ -158,14 +157,12 @@ static void amd_enable_serializing_lfence()
unsigned const family = Hw::Vendor::get_family(); unsigned const family = Hw::Vendor::get_family();
/* In family 0Fh and 11h, lfence is always dispatch serializing */ /*
if ((family == 0x10) || * In family 0Fh and 11h, lfence is always dispatch serializing and
(family == 0x12) || * "AMD plans support for this MSR and access to this bit for all future
/* * processors." from family 14h on.
* "AMD plans support for this MSR and access to this bit for all */
* future processors." if ((family == 0x10) || (family == 0x12) || (family >= 0x14)) {
*/
(family >= 0x14)) {
Cpu::Amd_lfence::access_t amd_lfence = Cpu::Amd_lfence::read(); Cpu::Amd_lfence::access_t amd_lfence = Cpu::Amd_lfence::read();
Cpu::Amd_lfence::Enable_dispatch_serializing::set(amd_lfence); Cpu::Amd_lfence::Enable_dispatch_serializing::set(amd_lfence);
Cpu::Amd_lfence::write(amd_lfence); Cpu::Amd_lfence::write(amd_lfence);
@@ -358,7 +355,7 @@ Bootstrap::Platform::Board::Board()
} }
/* /*
* Enable serializing lfence on supported AMD processors. * Enable serializing lfence on supported AMD processors
* *
* For APs this will be set up later, but we need it already to obtain * For APs this will be set up later, but we need it already to obtain
* the most acurate results when calibrating the TSC frequency. * the most acurate results when calibrating the TSC frequency.

3
repos/base-hw/src/include/hw/spec/x86_64/x86_64.h
View File

@@ -110,7 +110,8 @@ public:
struct Hw::Tsc struct Hw::Tsc
{ {
/* /*
* Provide serialized access to the Timestamp Counter. * Provide serialized access to the Timestamp Counter
*
* See #5430 for more information. * See #5430 for more information.
*/ */
static Genode::uint64_t rdtsc() static Genode::uint64_t rdtsc()