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fixup "hw: always serialize rdtsc reads" (final cosmetic touches)
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@@ -131,7 +131,7 @@ static void disable_pit()
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PIT_MODE = 0x43,
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};
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/**
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/*
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* Disable PIT timer channel. This is necessary since BIOS sets up
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* channel 0 to fire periodically.
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*/
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@@ -142,12 +142,11 @@ static void disable_pit()
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/*
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* Enable dispatch serializing lfence instruction on AMD processors.
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* Enable dispatch serializing lfence instruction on AMD processors
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*
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* See:
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* Software techniques for managing speculation on AMD processors
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* Revision 5.09.23
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* Mitigation G-2
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* See Software techniques for managing speculation on AMD processors
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* Revision 5.09.23
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* Mitigation G-2
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*/
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static void amd_enable_serializing_lfence()
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{
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@@ -158,14 +157,12 @@ static void amd_enable_serializing_lfence()
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unsigned const family = Hw::Vendor::get_family();
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/* In family 0Fh and 11h, lfence is always dispatch serializing */
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if ((family == 0x10) ||
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(family == 0x12) ||
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/*
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* "AMD plans support for this MSR and access to this bit for all
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* future processors."
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*/
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(family >= 0x14)) {
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/*
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* In family 0Fh and 11h, lfence is always dispatch serializing and
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* "AMD plans support for this MSR and access to this bit for all future
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* processors." from family 14h on.
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*/
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if ((family == 0x10) || (family == 0x12) || (family >= 0x14)) {
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Cpu::Amd_lfence::access_t amd_lfence = Cpu::Amd_lfence::read();
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Cpu::Amd_lfence::Enable_dispatch_serializing::set(amd_lfence);
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Cpu::Amd_lfence::write(amd_lfence);
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@@ -358,7 +355,7 @@ Bootstrap::Platform::Board::Board()
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}
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/*
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* Enable serializing lfence on supported AMD processors.
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* Enable serializing lfence on supported AMD processors
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*
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* For APs this will be set up later, but we need it already to obtain
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* the most acurate results when calibrating the TSC frequency.
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@@ -110,7 +110,8 @@ public:
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struct Hw::Tsc
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{
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/*
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* Provide serialized access to the Timestamp Counter.
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* Provide serialized access to the Timestamp Counter
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*
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* See #5430 for more information.
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*/
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static Genode::uint64_t rdtsc()
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